1. Field of the Invention
The present invention relates to signal processing, and, in particular, to error-correction encoding and decoding techniques such as low-density parity-check (LDPC) encoding and decoding.
2. Description of the Related Art
In decoding a codeword, a low-density parity-check (LDPC) decoder may encounter one or more trapping sets that prevent the decoder from properly decoding the codeword. Trapping sets, which represent subgraphs in a Tanner graph of an LDPC code, typically have a strong influence on error-floor characteristics of the LDPC code because a trapping set may force the decoder to converge to an incorrect result. To improve error-floor characteristics, an LDPC decoder may employ different techniques to break dominant trapping sets (i.e., trapping sets typically having the most-significant influence on error-floor characteristics). These dominant trapping sets vary widely based on the operating conditions of the decoder, such as decoder alphabet, decoder algorithm, decoder check-node unit update, channel conditions, and signal conditions.